Since the late 1960's, a new generation of dynamic random access integrated memory circuits has been developed approximately every four years. Each generation has been characterized by a halving of device dimensions, resulting in a four-fold density increase over the preceding generation. Increases in DRAM circuit density have been historically limited by two factors: the problem of maintaining cell capacitance as cell area is decreased, and the resolution capability of available photolithographic equipment.
Three-dimensional cell designs and high-performance cell dielectrics are being utilized to maintain sufficient cell capacitance as cell horizontal dimensions are shrunk. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is directly related to its resolution capability. The sum of minimum feature width (F) and minimum space width (S) producible with a given piece of photolithographic equipment is referred to in this disclosure as "minimum pitch". Since, for practical purposes, F can be considered to be equal to S, minimum pitch is, therefore, approximately equal to double the minimum feature width, or 2F. Using contemporary photolithography techniques, one minimum-width line (feature) and one minimum-width space may be defined for a given minimum pitch.
In a contemporary DRAM cell of conventional design, at least two rowlines and two spaces between rowlines (a total width of 4F) must be created within the X-direction width of a cell. Additional X-direction width (typically 2F) is required for the construction of a cell capacitor. This equates to a minimum X-direction width of 6F. In the Y-direction, a digit line and a space between digit lines are required. Added to this minimum total of 2F is at least another width of 1F, additional space required to provide adequate cell capacitance. Thus, total cell area is 6F (the X-direction width) multiplied by 3F (the Y-direction width), or 18F.sup.2. The actual cell size of contemporary, commercially available DRAMs varies from 16F.sup.2 to 20F.sup.2, depending on the actual cell structure and how much horizontal area it requires. Contemporary 4-megabit DRAMs are typically fabricated with photolithographic processes having 0.7 .mu.m minimum feature resolution (i.e., F=0.7 .mu.m and minimum pitch=2F or 1.4 .mu. m. Thus, the area of an average 18F.sup.2 4-megabit DRAM cell is about 9 .mu.m.sup.2.
It has long been recognized, by those skilled in the fabrication of integrated circuits, that vertical film layers as thin as 0.01 .mu.M can be grown with a high degree of accuracy. Isolated vertical film layer segments may be formed by depositing an expendable layer on a substrate, masking and etching the expendable layer down to the substrate such that expendable layer remnants having vertical sidewalls are created, blanket depositing a thin spacer layer over the substrate and expendable layer remnants, performing an anisotropic etch to create spacers on the sidewalls of the expendable layer, and then etching away the expendable layer remnants to leave the spacers. In the early 1980s, Seiki Ogura, Christopher F. Codella, Nivo Rovedo, Joseph F. Shepard and Jacob Riseman of IBM Corp. used this spacer technique to create a half-micron-width MOSFET gate. If a process could be devised in which thin vertical film layers, created using the aforementioned technique, were consistently and repeatedly used to define horizontal dimensions within an integrated circuit, minimum pitch could be dramatically reduced at a given level of photolithographic resolution, resulting in increased circuit density equal to the square of the reciprocal of the reduction factor.